The technical difference: higher numerical aperture, smaller patterns
High-NA EUV is an evolution of extreme ultraviolet lithography, the technique that transfers microscopic patterns onto layers of a silicon wafer. NA stands for numerical aperture; in simplified terms, it describes the optical system’s ability to collect and focus light. In ASML’s earlier EUV scanners, the numerical aperture is 0.33; in the High-NA EXE platform, it reaches 0.55. This is not a new kind of light: the platform still uses 13.5-nanometer EUV light, but changes the optical system so it can project smaller details. Source: ASML
ASML specifies an 8-nanometer resolution for its TWINSCAN EXE:5000 system and compares this capability with the NXE generation: a single exposure can print features 1.7 times smaller and, under suitable conditions, enable higher transistor densities. These are manufacturer-stated imaging capabilities, not an automatic description of every chip made or of its final performance. A commercial node—for example, 18A—also does not literally correspond to a single transistor dimension: the process name alone is not enough to infer the resolution of each layer. Source: ASML
The potential industrial benefit is to resolve certain patterns with fewer exposures or multipatterning steps. Reducing operations could shorten manufacturing cycle time and lower some sources of complexity, but the economic outcome also depends on other factors: the scanner’s effective throughput, availability, exposure dose, defects, mask cost, and process stability. Therefore, higher resolution is a useful physical capability, not by itself a guarantee of cheaper or higher-yielding chips. ASML describes reducing steps as a possible platform advantage, not as a universal savings figure. Source: ASML
The announced milestone and what it actually counts
On September 7, 2026, Intel Foundry and ASML reported that more than one million wafers had been processed using High-NA EUV. The decisive detail is what makes up that total: it includes tool certification and early testing, research and development, and volume production on selected layers of some Intel Core Ultra Series 3 processors, codenamed Panther Lake. It is therefore not one million finished commercial wafers processed exclusively with High-NA. Source: Intel
The distinction matters because a wafer can pass through the scanner for different purposes, and a product wafer requires multiple manufacturing stages. The announcement does not provide a numerical breakdown between test, development, and volume-manufacturing wafers; nor does it specify how many High-NA exposures each wafer in the count received. The figure thus certifies accumulated activity on the platform, according to the companies, but it does not let us calculate how many saleable processors came out of it or what proportion of the total represents production. One million counts wafers processed, not millions of finished chips. Source: Intel
Intel and ASML add that the technology is already being used in high-volume production for certain layers of some Panther Lake processors, and that Intel 18A layers made with High-NA deliver yield that, according to their comparison, matches or exceeds comparable layers printed using the 0.33-NA NXE platform. The announcement does not publish detailed metrics that would allow this comparison to be audited: it provides no wafer-yield rates, sample sizes, defects per layer, or complete methodology. This is relevant information about production use, but quantitative assessment still depends on information the announcement does not provide. Source: Intel
What can be inferred about industrial readiness
Although the count does not settle process economics, accumulating operations on new tools can help uncover integration problems and develop manufacturing routines. Certification and testing help tune the equipment; research helps characterize materials and patterns; product manufacturing adds the requirement to repeat a process within an industrial line. The companies’ report of activity across all three areas suggests that High-NA has progressed beyond an isolated demonstration. This is a limited inference from the range of uses they reported, not independent validation of the maturity of the entire technology. Source: Intel
Intel also says that layer overlay, wafer throughput, and tool availability are meeting its expectations. These are relevant operational indicators: overlay describes alignment between successive patterns; throughput describes how many wafers a system can process in a given period; and availability indicates how much time it is ready to operate. But “meeting expectations” gives neither measured values nor a point of comparison. It does not establish the cost of each layer, whether productivity matches mature scanners, or how results vary across shifts, factories, and designs. Source: Intel
To assess the move from qualification to broader adoption, comparable data series would be needed: output per tool and time period, actual operating time, defects and chip yield, cost per layer, and the number of layers using High-NA in each product. It would also be useful to distinguish testing and development results from those for delivered manufacturing. Without this breakdown, the milestone serves as a signal of accumulated experience and industrial activity, not a complete measure of High-NA’s competitiveness against conventional EUV. That limitation does not invalidate the announcement: it precisely defines what can be concluded from it.
Higher resolution also means solving the mask-field fit
High-NA optics use a smaller exposure field than the previous generation. According to ASML, the anamorphic mirror design allows the numerical aperture to increase while retaining the reticle format commonly used today, but it halves the exposure field in one direction. For designs that need a larger field, one possible solution is to split the pattern and join the exposures using a stitching technique. Joining them adds design, control, and registration requirements; Intel and ASML’s announcement confirms that they are developing this route with the current six-inch mask format. Sources: ASML and Intel
Intel says companies can make use of High-NA by designing within the available field or using its stitching solutions and process design kit. At the same time, Intel and ASML are working with mask, automation, electronic design, and materials suppliers to advance a transition to larger-format reticles, identified in the announcement as 6 × 12 inches. The coexistence of these two routes shows that adoption does not depend on the scanner alone: tools, chip design, masks, and factory processes must work together. The announcement presents the larger format as an area of development and industrial coordination, not as a condition already implemented universally. Source: ASML
Consequently, High-NA may be useful before it is extended to every layer or every manufacturer. Companies can select the layers where the extra resolution justifies integration complexity and cost, while keeping others on established techniques. Intel describes precisely this kind of use on selected layers of certain products. Whether that strategy is right for a particular design is an engineering and process-economics decision; the announcement does not show that the same combination is optimal for every chip. Source: Intel
How to read the announcement without confusing progress with scale
The soundest reading combines three levels of evidence. First, the manufacturer’s technical specification: ASML documents that EXE raises NA to 0.55 and offers a nominal resolution of 8 nanometers. Second, the joint announcement: Intel and ASML put the milestone at more than one million wafers and explain that the total mixes testing, R&D, and volume production on some layers. Third, the process data needed to measure economics and quality, which the announcement does not break out. Keeping these evidence layers separate avoids turning an activity figure into a conclusion about commercial yield. Sources: ASML and Intel
It is also worth paying attention to the scope of the comparisons. “Matches or exceeds” refers to the companies’ claim about certain layers versus comparable layers made with NXE; it does not mean overall processor performance, total production cost, or the entire High-NA platform is superior. Similarly, saying there is volume production on selected layers does not mean that every layer in the product is exposed with High-NA. Precision about scope matters just as much as the headline figure when interpreting a manufacturing advance.
In short, the million reported on September 7, 2026, supports the view that Intel has accumulated substantial use of High-NA tools across validation, research, and manufacturing of some product layers. It does not, by itself, quantify commercial volume, chip yield, costs, or the technology’s spread among manufacturers. The balanced conclusion is that High-NA has entered a specific productive use at Intel, while questions remain about its quantitative performance and economics at broader scale. That is a significant industrial advance, but a more limited one than the idea that a general transition has already been completed.